A priority-interrupt system is found in most modern computer systems. These may be implemented in hardware, software, or in a combination of hardware and software. These priority-interrupt systems can respond to externally or internally generated events, operating system calls, or other trigger events in a system.
Typically, a priority-interrupt system has multiple input signals. These signals may come from a variety of internal and external sources. When a trigger event occurs, a processor of the system executes a code segment associated with an active signal of the input signals. The time required from activation of an interrupt input signal to execution of a code segment associated with that input is known as interrupt latency.
There are generally multiple code segments available for execution, each may be located through a pointer known as an interrupt vector. Each code segment is associated with a particular signal of the input signals. The process of branching to code at interrupt vectors is known as vectoring.
Since input signals generally relate to system functions that can occur at different rates, it is generally desirable to prioritize the input signals. Priority interrupt systems prioritize the input signals such that, when multiple input signals occur, the code segment first executed is associated with the highest priority active input, while code segments associated with lower priority inputs may execute later. This is typically done by passing the input signals through a priority encoder to generate an interrupt vector associated with the highest priority active signal present at the time.
Priority encoders of hardware and software construction are known. Computer hardware often has special instructions provided for use in software priority encoders; for example there may be an instruction that generates a binary number corresponding with the most significant active bit of a word. Many microcontrollers, including those of the Intel 8096 family, provide hardware priority encoders for mapping signals to interrupt vectors.
Hardware priority encoders typically embody a fixed priority scheme. With these encoders, prioritization of interrupts is performed according to an integrated circuit designer's best guess, at the time a processor integrated circuit is designed, of appropriate priority for each interrupt input. Modern microcontroller integrated circuits are, however, often used in applications very different from those contemplated at the time the integrated circuit is designed. For example, the Intel 8061, parent of the Intel 8096/80196/80296 and Ford EEC-4 processor families, was developed to control a gasoline engine. Members of this processor family have been used in hundreds of products ranging from automatic transmissions, active suspensions, missile autopilots, printers, and disk drives to microwave ovens; the original integrated circuit designer's priority assignments are not optimum for all systems.
Other computer systems and microcontrollers are known where multiple input signals are brought to an interrupt status register, but where hardware encoding is not provided, or is provided over fewer input signals than required in a particular system. This may occur, for example, where interrupt sources not contemplated by the original integrated circuit designers are present in a system.
In either event, it is desirable to prioritize interrupts and generate vectors in software or firmware. Since large numbers of interrupts occur in typical microcontroller and computer systems, it is important that the overhead steps of encoding multiple inputs into interrupt vectors be performed quickly.